1. Field of the Invention
The present invention relates to a cathode device, and in particularly, to a cathode device referred to as a small-sized field emission cold cathode. The present invention also relates to a method for fabricating a cathode device using etching.
2. Description of the Related Art
A small-sized field emission cold cathode comprises an emitter tip or a plurality of emitter tips and a gate electrode layer. A typical cathode device is shown in FIG. 28 of the attached drawings. In FIG. 28, the cathode device comprises an emitter tip 2 formed on a substrate 1 and having a conical tip end portion 2A, and a gate electrode layer 4 formed above the substrate 1 and having an opening 4A through which the tip end portion 2A of the emitter tip 2 is exposed. An insulating layer 3 is provided between the substrate 1 and the gate electrode layer 4. When the voltage is applied between the stem portion 2B of the emitter tip 2 and the gate electrode layer 4, a strong electric field is developed between the tip end portion 2A of the emitter tip 2 and the inner circumferential wall 4B of the opening 4A of the gate electrode layer 4. Electrons are thus emitted from the tip end portion 2A of the emitter tip 2.
The small-sized field emission cold cathode is a source of emitted electrons and is used in a display device or in a micro-vacuum-tube. The small-sized field emission cold cathode has high electron mobility of and can operate at a high speed. Also, the small-sized field emission cold cathode can operate at a high temperature and has high durability against radiation. Accordingly, it is expected that the small-sized field-emission cold cathode can be used in the above described applications and also in a variety fields such as microwave elements, super high speed calculators, active devices for use in a radioactive environment in space or in a reactor, or in active devices for use in a high-temperature environment.
It is known that the foregoing cathode device can be fabricated using etching. For example, a typical process for fabricating the cathode device on a silicon substrate 1 is shown in FIGS. 29A to 29D in the attached drawings. A mask 51 having a diameter corresponding to the shape of the emitter tip 2 is formed on the substrate (FIG. 29A), and etching is performed so that the unmasked portion of the surface of the substrate 1 is removed while the portion of the substrate 1 under the mask 51 is left in the form of a peak (FIG. 29B). The peak-shaped portion becomes the emitter tip 2. Thereafter, the substrate 1 is subjected to a thermal oxidation while the mask 51 is maintained on the emitter tip 2, with the result that an oxide diffuses inside the emitter tip 2 and an oxide layer 52 is formed on the surface of the emitter tip 2 (FIG. 29C). If the oxide layer 52 is removed at the later step, the emitter tip 2 having the sharper tip end portion 2A appears.
Thereafter, the insulating layer 3 is formed while the mask 51 is maintained on the emitter tip 2. Since the emitter tip 2 is covered by the mask 51, the insulating layer 3 is formed on the unmasked portion of the substrate 1 and on the mask 51. The gate electrode layer 4 is then formed on the insulating layer 3 by vapor deposition or the like (FIG. 29D). The gate electrode layer 4 is placed on the insulating layer 3 on the substrate 1 and on the insulating layer 3 on the mask 51. When the mask 51 is finally removed, the insulating layer 3 and the gate electrode layer 4 on the mask 51 are removed simultaneously with the mask 51. The oxide layer 52 around the emitter tip 2 is also removed. Thus, openings 4A corresponding to the mask 51 are formed in the insulating layer 3 and the gate electrode layer 4 and the emitter tip 2 is exposed through the openings 4A, as shown in FIG. 28.
In the cathode device fabricated as described above, the size "D" of a portion of the emitter tip 2 at the juncture (bottom) thereof with the substrate 1 is smaller than the size of the mask 51. The size "d" of the opening 4A of the gate electrode layer 4 depends on that of the mask 51. Therefore, the size "D" of the juncture portion of the emitter tip 2 is smaller than the size "d" of the opening 4A of the gate electrode layer 4 (D&lt;d). In practice, when the insulating layer 3 is formed by vapor deposition, the contour of the insulating layer 3 on the mask 51 diverges as it piles up, as shown in FIG. 30. In some cases, a parasitically growing collar 10 is formed on the shoulder of the emitter tip 2. Upon the subsequent formation of the gate electrode layer 4, the opening 4A of the gate electrode layer 4 becomes larger in diameter than the mask 51. When the mask 51, the insulating layer 3 thereon, and the parasitically growing collar 10 are then removed, the size "D" of the juncture portion of the emitter tip 2 is considerably smaller than the size "d" of the opening 4A of the gate electrode layer 4 (D&lt;d), as shown in FIG. 31. In addition, it is difficult to make a mask 51 having a diameter smaller than, for example, approximately 1 .mu.m using current photolithographic technology.